1. Field of the Invention
The present invention relates to an operational amplification circuit, and, more particularly, to an operational amplification circuit capable of driving a high load and suitable for an apparatus such as a portable telephone, in which a voice is amplification object.
2. Description of the Related Art
Conventionally, when an operational amplification circuit capable of driving a high load is structured, a push-pull type amplification circuit is used, however, in this operational amplification circuit, a phenomenon, in which an output waveform is distorted, called a crossover distortion occurs. Therefore, contrivances are given to reduce a crossover distortion to the an operational amplification circuit used for amplifying a signal such as a voice, which requires an accurate wave amplification.
For instance, Japanese Patent Application Laid-Open No. 4-310006 in 1992 discloses an operational amplification circuit showing this structure. As shown in FIG. 3, an operational amplification circuit 30 consists of a first differential amplification circuit 31, a second amplification circuit 32, and an output amplification circuit 35. The operational amplification circuit 30 is also provided with phase compensation circuits 33, 34 each consisting of a capacitor C and a resistance R. The phase compensation circuits 33, 34 are implemented to prevent the operational amplification circuit 30 from oscillating and have no relation to an amplification action, so that no explanation is given for these circuits.
The first differential amplification circuit 31 consists of P channel metal oxide semiconductor field effect transistors (hereinafter, called PMOS) 81, 82 and N channel metal oxide semiconductor field effect transistors (hereinafter, called NMOS) 83-85.
Gates of the NMOSes 83, 84 are connected with an IN1 and an IN2, respectively, which are input terminals of the operational amplification circuit 30. Sources of the NMOSes 83, 84 are connected with a drain of the NMOS 85 of which a source is connected with the GND and a gate is supplied with a control signal for setting a bias voltage. Drains of the NMOSes 83, 84 are connected with drains of the PMOSes 81, 82, respectively. Sources of the PMOSes 81, 82 are connected with the V.sub.DD and gates of the PMOSes 81, 82 are connected with drain of the PMOS 81. And, an output is obtained from a connection point (node N8) between the drain of the PMOS 82 and the drain of the NMOS 84.
That is, the differential amplification circuit 31 generates a voltage in accordance with the voltage difference between the IN1 and the IN2 at the node N8. For instance, when the voltage of the IN1 is higher than that of the IN2, a voltage close to the V.sub.DD level is outputted from the node N8, and when the voltage of the IN2 is higher than that of the IN1, a voltage close to the GND level is outputted from the node N8.
The second differential amplification circuit 32 consists of NMOSes 89, 90 and PMOSes 86-88. Gates of the PMOSes 87, 88 are connected with the IN1 and the IN2, respectively. Sources of the PMOSes 87, 88 are connected with a drain of the NMOS 86 of which a source is connected with the V.sub.DD and a gate is supplied with a control signal for controlling a bias voltage. Drains of the PMOSes 87, 88 are connected with drains of the NMOSes 89, 90, respectively. Sources of the NMOSes 89, 90 are connected with the GND and gates of the NMOSes 89, 90 are connected with a drain of the NMOS 89. And, an output is obtained from a connection point (node N9) between drain of the NMOS 90 and the drain of the PMOS 88.
That is, the second differential amplification circuit 32 operates complementally with the first differential amplification circuit 31. In the second differential amplification circuit 31, when the voltage of the IN1 is higher than that of the IN2, a voltage close to the V.sub.DD level is outputted from the node N9, and when the voltage of the IN1 is lower than that of the IN2, a voltage close to the V.sub.DD level is outputted from the node N9.
The output amplification circuit 35 consists of a PMOS 91, a NMOS 92 and a resistance RX. A source of the PMOS 91 and a source of the NMOS 92 are connected with the V.sub.DD and the GND, respectively. A drain of the PMOS 91 is connected with a drain of the NMOS 92, and the connection point therebetween is connected with the output terminal OUT for the operational amplification circuit 30. A gate of the PMOS 91 and a gate of the NMOS 92 are connected with the node N8 in the first differential amplification circuit 31 and the node N9 in the second differential amplification circuit 32, respectively.
Now, a crossover distortion occurs when the both MOSes in the output amplification circuit 35 transit simultaneously between an on-state and an off-state. As described above, in the operational amplification circuit 30, signals are inputted from independent circuits to the gate of the PMOS 91 and the gate of the NMOS 92 in the output amplification circuit 35, respectively. Thus, the operational amplification circuit 30 is easy to design so as not to occur a crossover distortion.
Moreover, in the operational circuit 30, the resistance RX is arranged between the gates of the PMOS 91 and the NMOS 92 in the output amplification circuit 35, therefore, when one of the differential amplification circuits 31, 32 stops the operation thereof because a low power voltage is used, an output from an operative differential amplification circuit is supplied to the both MOSes in the output amplification circuit 35. Therefore, the operational amplification circuit 30 is normally operative in that case.
However, the operational amplification circuit 30 is provided with a resistance so as to be operative normally under a low power voltage. As the result, there is a problem in that a large area is needed for fabricating the operational amplification circuit 30. And, when the operational amplification circuit 30 drives a high load under a low power voltage, a current runs through the resistance RX, so that there is another problem in that a consumption power increase.